Such an arrangement is known for CCD shift registers clocked in two phases. In this prior art CCD circuitry pairs of first-polysilicon-layer and second-polysilicon-layer gate electrode structures cross adjacent charge transfer channels. The first-layer and second-layer gate electrode structures in each pair meander back and forth respective to each other to appear in opposite order in adjacent charge transfer channels, each cross-over/cross-under taking place over a channel stop between adjacent charge transfer channels. Both the gate electrodes in each pair are connected to receive the same phase of clocking signal, and each succeeding pair of gate electrodes receives the phase of two-phase clocking signal complementary to the phase received by the preceding pair. The second-polysilicon-layer gate electrodes have barrier implantations into the substrate beneath them to determine the direction of charge transfer from the first-polysilicon-layer gate electrode towards the second-polysilicon-layer electrode for each pair of gate electrodes. Because of the cross-meandering of the pair of electrodes so they appear in opposite order in adjacent charge transfer channels, charge transfer is in opposing directions in adjacent charge transfer channels.
It is desirable to clock CCD shift registers in at least three phases, however, to obtain the best yields of usable devices during semiconductor device manufacturing. Short-throughs between overlapping polysilicon layers which render a two-phase CCD shift register useless can be tolerated in multiple-phase CCD shift registers. CCD shift registers with multiple-phase clocking also have greater dynamic range since the fraction of the charge transfer channel taken up by potential barriers is smaller respective to the fraction of the channel in which potential wells are available for holding charge.
Control of the direction of charge transfer in CCD shift registers using multiple-phase clocking signals is not normally determined by barrier implantations, but rather by the order in which the gate electrodes having different phases of clocking appear across the charge transfer channel. Multiple-phase-clocked CCD shift registers can be clocked in opposite phase sequence to reverse the direction of charge transfer, which is not possible with two-phase-clocked CCD shift registers using implanted barriers. Conventionally, clocking phases are denominated by ordinal numbers indicative of their normal order of succession in time.
Gate electrodes which meander respective to each other along their widths, the present inventor points out, can be used to re-order the appearance of clock phases to be different in adjoining charge transfer channels. A gate electrode can cross over one, or perhaps two, other gate electrodes in the area of the channel stop separating adjacent charge transfer channels. However, the number of layers of polysilicon available for gate electrode structures is usually limited to three to keep the number of manufacturing steps within reason. It is desirable that cross-overs and cross-unders can be kept in the same layer of polysilicon as the gate electrodes being connected, to avoid having to ohmically contact a top-metallization cross-over. So, lay-out problems are difficult to solve.
In CCD imagers where image integration takes place in parallel CCD shift registers, preferably the gate electrodes are arranged such that the centers of picture elements ("pixels") integrated in adjacent charge transfer channels are aligned in straight lines normal to the charge transfer channels. This imposes another constraint on lay-out.